The present invention relates to a method and apparatus for combining different bus-width architectures of a memory device on a single semiconductor chip and, more particularly, to selecting one of a plurality of bus width configurations of a memory device using a logic option circuit.
Memory subsystems for computers and other processor systems provide many memory devices on a common bus to allow larger storage and transmission capacities than can be obtained with a single memory device. In such systems, one or more integrated circuit chips contain the memory devices and permit connection of the memory devices to a data bus. The data bus facilitates the transmission of data between memory devices and other system components, for example a processor.
The data bus commonly consists of a finite number of data paths, the finite number usually being dubbed the xe2x80x9cbus width.xe2x80x9d For most memory subsystems, the bus width is predetermined and fixed, meaning that each of the memory devices must be capable of transmitting and receiving data using a data bus of the predetermined bus width.
Due to the high cost of designing and developing integrated circuit chips, chip manufacturers often will design and produce a single chip having multiple architectures or configurations. Thus the same chip design may be mass-produced and used for a variety of applications, taking advantage of economies of scale and other cost-saving manufacturing techniques. For a chip of this type, after or near the end of fabrication the chip must be configured for use with its intended application.
For chips containing memory devices, a common parameter that varies between applications is the data bus width of the memory subsystem. Some exemplary memory subsystems use a data bus width of 18 bits, others 36 bits, and still others 72 bits. However, these exemplary values are not required and any number of bits may be used for the data bus width. In order to mass-produce memory devices capable of use in a variety of systems having different bus widths, chip manufacturers will often design and fabricate a single chip capable of transmitting and receiving data using one of several bus width configurations. For example, a single chip may be designed to interact with a data bus having a bus width of either 72 bits or 36 bits, depending on the way the chip is configured following fabrication.
The technique used to configure a chip capable of multiple configurations is often termed an xe2x80x9coption.xe2x80x9d Exemplary conventional options include xe2x80x9cbondxe2x80x9d, xe2x80x9cviaxe2x80x9d and xe2x80x9cmetalxe2x80x9d options. The bond, via and metal options each involve different methods of hard-wiring a memory device so that certain logic circuits and data paths are activated to cause the chip to function according to the chosen configuration. For example, a laser option may involve blowing laser fuses on the chip to activate those portions of the chip circuitry that cause the memory devices on the chip to function correctly when connected with a data bus having a width of 36 bits. As another example, a typical metal option may include depositing a small amount of conductive metal in specific locations on the chip to form electrical connections sufficient to cause the memory devices on the chip to function correctly when connected to a data bus having a width of 72 bits.
Bond, via and metal options typically involve adding gates and/or multiplexing circuits in paths where speed of data throughput is critical to the operation of the memory device. The gates and/or multiplexing units usually impose a speed penalty, making their use less desirable. Also, bond, via and metal options often are irreversible, meaning that once the decision is made to use one configuration, the chip may not thereafter be re-configured for use in a different application. In addition, via and metal options usually require that configuration decisions be made at the end of fabrication or immediately following fabrication of the chip, reducing user control of configuration options and thus reducing flexibility.
Therefore, there is a strong desire and need to develop a design for a memory device option that allows user configuration of the bus width at any time, the ability to easily reverse the option that is applied, while imposing a minimum speed penalty.
The present invention provides an apparatus and method for selecting one of a plurality of data bus width configurations of a memory device using a logic circuit. The logic circuit permits reversible selection of one of the available bus width configurations by a user or by the memory subsystem using specialized steering logic circuits and a data path for selecting among the available bus widths. This specialized steering logic circuitry may be embedded in the sense amplification circuitry of a memory device to minimize any speed penalty imposed on critical data paths.
The apparatus and method of the invention includes using a plurality of I/O circuits each connected to at least one of a plurality of memory arrays, and at least one address selection data path connected to at least one of the I/O circuits, wherein memory array data is accessed through a subset of the I/O circuits or though all of the I/O circuits, depending on the desired bus width. For a larger bus width, output paths for each of the I/O circuits are connected to bus lines of the memory system data bus. For a smaller bus width, only the output paths of a subset of the I/O circuits are connected to the bus lines of the memory system data bus.
In one aspect of the invention, a logic circuit is provided wherein a first data bus width may be used to access memory array data through the plurality of I/O circuits when a first selection signal is received on the address selection data path, and a second data bus width may be used to access memory array data through the plurality of I/O circuits when a second selection signal is received on the address selection data path.
In another aspect of the invention, a logic circuit is provided wherein each of the I/O circuits includes data paths for accessing data of more than one of the memory arrays and a select logic unit that indicates which of the more than one memory arrays should be accessed by the I/O circuit. The select logic unit includes an input select logic data path for user or system selection of which of the more than one memory arrays should be accessed by the I/O circuit.
In another aspect of the invention, a logic circuit is provided wherein the plurality of I/O circuits includes first and second I/O circuits, the first I/O circuit being connected to access data in a first memory array, the second I/O circuit being connected to access data in a second memory array or in the first memory array, the input select logic data path of the first I/O circuit selecting for output data from the first memory array and the input select logic data path of the second I/O circuit being connected to the address selection data path for selective output of data from the first memory array or the second memory array.
In another embodiment, a logic circuit is provided wherein the plurality of I/O circuits includes first and second I/O circuits, the first I/O circuit being connected to access data in a first memory array, the second I/O circuit being connected to access data in a second memory array or in the first memory array through the first I/O circuit, the input select logic data path of the first I/O circuit selecting for output data from the first memory array and the input select logic data path of the second I/O circuit being connected to the address selection data path for selective output of data from the first memory array or the second memory array. Data from the first memory array may therefore be output by the first I/O circuit or by the second I/O circuit after passing through the first I/O circuit.
In each of the embodiments described above, the first and second I/O circuits may be connected with a data bus of a fixed data bus width and the I/O circuits may be reversibly configured for use with that fixed data bus width. In a first, larger data bus width configuration, the address selection data path selects data from the second memory array for output from the second I/O circuit and both first and second I/O circuits are connected to the data bus. In a second, smaller data bus width configuration, the address selection data path sequentially selects data from the first and second memory arrays for output from the second I/O circuit, and only the second I/O circuit is connected to the data bus.